SEMI International Standards
Standards Locale: North America
Committee: Silicon Wafer
Place of Meeting: Intel, Santa Clara, CA
Date of Meeting: 04/02/2013
Meeting End Date: 04/02/2013
Recording SEMI Standards Staff: Kevin Nguyen
CER Posted to Web: 04/11/2013
Leadership Changes
None.
TC Chapter Structure Changes
None.
Ballot Results
Passed ballots and line items will be submitted to the ISC Audit & Review Subcommittee for procedural review.
Failed ballots and line items were returned to the originating task forces for re-work and re-balloting.
Document # | Document Title | Committee Action | A&R Forms for Approved Ballots |
5450A | Revision to SEMI M49-0912, Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 22 nm Technology Generations with Title Change to: Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 16 nm Technology Generations | Passed as balloted |  |
5559 | New Auxiliary Information: Interlaboratory Evaluation Of Nondestructive Method For Measuring The Edge Contour Of Silicon Wafers | Approved by committee |  |
Ratification Ballot Results
None.
Activities Approved by the GCS between meetings of TC Chapter meeting
None.
Authorized Activities
# | Type | SC/TF/WG | Details |
5543 | SNARF | Int’l Polished Wafer TF | Line Items Revision to SEMI M1, Specifications for Polished Single Crystal Silicon Wafers (SNARF was revised to allow additional line item changes) |
5583 | SNARF | Int’l Annealed Wafer TF | Revision of SEMI M57, Guide for Specifying Silicon Annealed Wafers |
Note: SNARFs and TFOFs are available for review on the SEMI Web site at:
http://downloads.semi.org/web/wstdsbal.nsf/TFOFSNARF
Authorized Ballots
# | When | SC/TF/WG | Details |
5543 | Cycle 4-2013 | Int’l Polished Wafer TF | Line Items Revision to SEMI M1, Specifications for Polished Single Crystal Silicon Wafers |
5541 | Cycle 4-2013 | Int’l SOI Wafer TF | Revision to SEMI M41-0707, Specification of Silicon-on-Insulator (SOI) for Power Device/ICs |
SNARF(s) Granted a One-Year Extension
None.
SNARF(s) Cancelled
None.
Standard(s) to receive Inactive Status
None.
Special Announcements of the Committee (Workshops, Programs, etc.)
The NA Silicon Wafer committee is planning a workshop on 450 mm Wafer to be held at SEMICON West on Wednesday, July 10, 2013. Tentative technical presentations include:
- Towards 450 mm Silicon Wafer - M. Goldstein (Intel)
- Edge Exclusion Proposal - K. Lee (Samsung/450GC)
- 450 mm Notchless Wafer - P. Lin (TSMC/450GC)
- Evolution of Wafer Geometry for Advanced Nodes - J. Sinha (KLA-Tencor)
Additional speakers from the Silicon Suppliers, IC Fab, and Equipment Manufacturers are being solicited. For question, please contact Jaydeep Sinha at [email protected] or Kevin Nguyen at [email protected]
For registration and agenda, please check www.semiconwest.org, under "Sessions/Events" click on "Standards".
Next Meeting
The next meeting will be in conjunction with SEMICON West Standards Meetings at the San Francisco Marriott Marquis in San Francisco, California. The committee will meet on Tuesday, July 9, 2013 from 1:00 PM-5:00 PM. Check http://www.semi.org/node/45276 for the latest schedule including Task Force meetings.
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